The present invention relates to a MOS semiconductor dynamic random access memory employing stacked capacitor cells and a process of fabricating the same.
The state of the art to which the invention relates is exemplified in an Annex No. 1 of Nikkei Micro Device "Jitsuyouka ni Mukete Shidousuru 4MDRAM no Zenbou (The Entire Picture of 4Mbit DRAM Starting for Commercialization)"pp. 117 to 130, and pp. 165 to 174, (May 1687).
FIG. 1 shows an example of a process of fabrication of such a conventional dynamic random access memory device (semiconductor memory integrated circuit device) employing stacked capacitor cells. The memory device comprises a memory cell area in which a plurality of memory cells are arranged in rows and columns to form one or more matrices, and a peripheral area outside of the cell area. In FIG. 1, part of the cell area containing a single memory cell is shown at (a) to (e) and part of the peripheral area is shown at (a'), (d') and (e').
Formed on a substrate 1 are an isolation field oxide film 2, a gate insulation film 3, a gate electrode 4, sidewall insulating films 5, a transistor comprising impurity diffusion regions 6 of a relatively low concentration (10.sup.17 to 10.sup.19 /cm.sup.3) and of the conductivity type opposite to that of the substrate 1, and an impurity diffusion regions 7 (hereinafter referred to as a high-concentration diffusion region) of a relatively high concentration and of the same conductivity type as the impurity diffusion region 6, and an insulating film 8 covering the entire surface. The resultant structure is shown at (a) and (a') in FIG. 1. During the above-described steps, known oxidation and diffusion processes can be utilized. The gate electrode 4 also serves as a word line and one of the high concentration diffusion regions 7 serves also as a data storage capacitor.
Next, a contact hole 9 for connection of the lower electrode of the stacked capacitor to one of the high concentration diffusion regions 7 is formed by photolithography (comprising exposure, development and etching). The resultant structure is shown at (b) in FIG. 1. The peripheral areais unchanged.
Then, a lower electrode 10 which will become the charge storage part of the stacked capacitor is formed by known photolithography. The resultant structure is shown at (c) in FIG. 1. The lower electrode 10 can be formed of polysilicon of the same conductivity type as the high-concentration diffusion region 7. The peripheral area is again unchanged.
Subsequently, a dielectric material film 11 is deposited over the entire surface of the structure shown at (c) and (a') in FIG. 1, and an upper electrode 12 of the stacked capacitor is formed over the entire surface into a desired pattern by means of known photolithography. The resultant structure is shown at (d) and (d') in FIG. 1. The upper electrode 12 is typically formed of polysilicon of the same kind as the lower electrode 10.
Although the dielectric material film 11 is shown to remain over the entire surface, it may be removed at parts other than underneath the upper electrode 12.
Finally, an inter-layer insulating layer 13, a metal wiring conductor 14 and a passivation insulating film 15 are formed. A contact hole 16 for connection for a wiring metal conductor 14' for providing a predetermined voltage to the capacitor upper electrode 12 are formed, at the same time as the formation of the contact hole for connection with the metal conductor 14. The resultant structure is shown at (e) and (e') in FIG. 1.
With the above-described structure, the surface area of the electrodes 10 and 12 which extend along the principal plane of the substrate 1 places a limit to the reduction of the memory cell size and hence to the increase in the degree of integration (packing density).